Job Opening: Digital Design Engineer

NHanced Semiconductors seeks enthusiastic, talented engineers to contribute to the success of our products. As a digital design engineer, you will drive digital ASIC projects through all aspects of the work flow, from concept through device testing. You will be responsible for developing state-of-the-art ASICs, architecting solutions, writing specifications, RTL coding, synthesizing, and simulating logic designs destined for our next-generation solutions. You will bring your independence, creativity, and experience to a team of like-minded individuals that are committed to the quality of their designs. Working at NHanced Semiconductors, you will encounter design challenges that are out of the ordinary and work with highly focused and motivated engineers across different design disciplines to find creative solutions.

Qualifications

  • BS/MS in Computer Engineering or Electrical Engineering with 5+ years’ experience
  • US citizenship or permanent residency

Responsibilities

  • Create readable, synthesizable, maintainable RTL in Verilog or System Verilog
  • Interpret device requirements and write chip specifications
  • Specify and implement device test and validation logic
  • Support design verification, floor-planning, and back-end timing closure
  • Work with Place & Route team and analyze results
  • Work in a dynamic environment with aggressive schedules

Technical Skills

  • Knowledge of entire chip design process
    (DFT, DFM, control interfaces, I/O, clocking, power, etc.)
  • Proficiency in RTL coding with Verilog or System Verilog
  • Test bench creation and functional verification
  • Synthesis and static timing analysis
  • Strong scripting skills (Python, Bash, Tcl)
  • Familiarity with industry standard ASIC design tools:
    • Synopsys (DC, Primetime)
    • Cadence Suite (Genus, Tempus)
    • Siemens/Mentor (Questa/ModelSim)

Preferred Experience

  • Digital design and debug for ASICs or advanced FPGAs
  • High-speed designs, complex functions, multiple clock domains
  • Success meeting challenging ASIC or FPGA design cycles
  • Synthesis, CDC, STA, Formal Verification, and ECO flows
  • Interaction with different design disciplines
    (verification, physical implementation, etc.)
  • Experience with UVM
  • OpenFPGA design flows

Personal Skills

  • Strong work ethic
  • Organized, creative, motivated
  • Independent learner
  • Multitask in a dynamic environment
  • Strong interpersonal and communication skills
  • Good command of written and verbal English

Job Location

Batavia, Illinois

More Information

For company description, benefits package, and application instructions see the Careers Page.