2.5D
An advanced packaging technology that bonds dies and/or chiplets onto an interposer within a single package
3D
An advanced packaging technology that incorporates multiple layers of circuitry into a single chip, integrated both vertically and horizontally
Carrier Wafer
A wafer that is used to hold dies or chiplets during intermediate steps, but is not a part of the finished device
Chip
A packaged integrated circuit
Chiplet
A very small die, designed to be mounted with other components on an interposer before packaging
D2D
Die to Die (also die-on-die) stacking: bonding and integrating individual dies atop one another
D2W
Die to Wafer (also die-on-wafer) stacking: bonding and integrating dies onto a wafer before dicing the wafer
DBI®
Direct Bond Interconnect – a bump-less hybrid bonding technology (developed by Ziptronix) practiced by NHanced
DBI Ultra
A DBI process that bonds dies rather than wafers
Dicing
Cutting a processed semiconductor wafer into separate dies
Die
An unpackaged integrated circuit; a rectangular piece cut (diced) from a processed wafer
Die on Die
See D2D
Die on Wafer
See D2W
Heterogeneous Integration
The combining of different types of integrated circuitry in a single device; differences may be in process, node, substrate, or function
IC
Integrated Circuit: an electronic circuit formed on a small piece of semiconducting material, performing the same function as a larger circuit made from discrete components
Integrated Circuit
See IC
Interconnect
Wires or traces that carry signals between the elements in an electronic device
Interposer
A small piece of semiconductor material (glass, silicon, or organic) built to host and interconnect two or more dies and/or chiplets in a single package
IoT
Internet of Things: the interconnection (via the Internet) of small devices embedded in everyday objects
Micro Transfer Printing (MTP)
A technology developed by X-Celeprint that uses a flexible stamp to transfer very small, thin chiplets from a source wafer to a target wafer for 3D stacking
Moore’s Law
An observation by Gordon Moore that the number of transistors per square inch on ICs doubled every year, and the prediction that they would continue to do so
More than Moore
A catch-all phrase for technologies that attempt to bypass Moore’s Law, creating smaller, faster, or more powerful circuitry without shrinking the size of the transistor
MTP
See Micro Transfer Printing
Node
See Process Node
Package
A plastic structure that holds an integrated circuit and provides connections to other components
Process Node
A standardized manufacturing process that defines the size of the electrical elements and how densely they can be packed together
Substrate
The semiconductor material underlying the circuitry of an IC, usually silicon
Through Silicon Via
See TSV
TSV
Through Silicon Via: a vertical electrical connection that pierces the substrate
Wafer
A disk of semiconductor material (usually silicon) on which circuits can be fabricated
Wafer on Wafer
See W2W
W2W
Wafer-to-Wafer (also wafer-on-wafer) stacking: bonding and integrating whole processed wafers atop one another before dicing the stack