Advanced Packaging in 2017

January: the month for resolutions, pronouncements, and predictions.  Major semiconductor players and publications are sounding off on the state of the industry.  The general tone is upbeat – and the hot news seems to be advanced packaging.  Here is a selection of recent quotes, with links to their sources:

“In packaging, the move toward 2.5D chip stacks that put logic, memory, digital, and analog die on a shared substrate looks exciting as a cool way to have heterogeneous silicon.”
Google Searches for Better Silicon
(Link to EE Times has been lost)

“The market is expected to be worth USD 170.46 billion in 2022, at a CAGR of 38.30% between 2016 and 2022. The drivers for this market are the increasing need for advanced architecture in electronic products, rising trend of miniaturization of electronic devices, and growing market for tablets, smartphones, and gaming devices.”
3D IC and 2.5D IC Packaging Market worth 170.46 Billion USD by 2022
(Link to Solid State Technology has been lost)

“as the IoT goes through its first phase of adoption, advanced packaging will play a major role, as the technology calls for the integration of MEMS, sensors, RF devices, analog, etc.”
What the Heterogeneous Integration Technology Roadmap Will Mean for 2017

“Advanced packaging is now an integral part of most scaling and functionality roadmaps.  By incorporating 2.5D, 3D, and wafer level chip scale packaging (WLCSP), both fan-in and fan-out technologies, manufacturers are able to meet consumer demand for miniaturization and increased functionality while reducing costs and improving performance.”
Addressing Advanced Packaging Challenges in 2017 and Beyond

“The 3DIC through-silicon via stacks packaging technique will be responsible for generating almost 75% of the market revenue by 2021, posting a CAGR of 45% … 2.5D silicon interposers manufactured using four-metal layer back-end-of-line process has achieved data rates up to 11.5 Gbps. These impressive statistics are pushing for the high adoption of the 2.5D interposers packaging technique.”
Global semiconductor chip packaging market dominated by 3DIC
(Link to Solid State Techology has been lost)

“The key requirements of modern day electronic devices are enhanced storage capability, low power requirements, efficient thermal management components, high-speed data transmission, high-speed data processing, high brightness lighting, connected and smart devices. These requirements from the consumer end of the supply chain are the key driving forces behind growth in 3D IC technology and its inherent market.”
Future Opportunities for 3D Integrated Circuits

 “Whether you call them chiplets, or dielets, heterogeneously integrating very small devices using some kind of silicon-based (or glass-based) interconnect fabric is a pretty terrific idea from a cost perspective, and also from a performance one.”
Outlook 2017: SoC Goes on a Dielet