Our Foundry 2.0 manufacturing model begins with dies sourced from traditional high-volume semiconductor foundries. As a third-party integrator, we don’t build the transistors themselves, so we don’t compete with the leading foundries; we work with them.

We combine the sourced building blocks in novel combinations using advanced packaging technologies like through silicon vias (TSVs), hybrid bonding, and glass or silicon interposers.

• TSVs: ratios up to 10:1, depth to 300µm
• Hybrid bonding: sub-micron alignment, die pitch down to 2µm
• Interposers: industry-leading 2µm line/space interconnect

Customers get the best of both worlds: their leading-edge chips are crafted into sophisticated, highly differentiated, heterogeneously integrated products at the volumes they need, and at 3X reduction in development costs.

• Wafer sizes from 50mm to 200mm
• Bond pad pitch down to 45µm
• Class 100 cleanroom
• Can process multi-layer stacks up to 2mm
• Wafer-to-wafer alignment +/- 1µm
• Die-to-wafer alignment +/- 0.2µm
• Die sizes 0.5 x 0.5mm to 26 x 33mm
• Low temperature processing (<170°C)

> Foundry 2.0™ Aims to Extend Moore’s Law

> Foundry 2.0™: A renaissance in innovation

> High-Tech Nexus Launched in Indiana

> NHanced Foundry 2.0™ on TV News

> Inside the World of Advanced Packaging

> Microwave Journal says we’re “Making the Impossible Possible”